2018-05-19 - email@example.com
- Update to new upstream release 20180519
* Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields.
* Added 7/ecx bit 16: 5-level paging.
* Improved 14/0/ecx descriptions.
* Added hypervisor leaf descriptions from Microsoft's
Hypervisor Top Level Functional Specification (Released
* Added CPUID features documented in PPR for AMD Family 17h
Model 01h B1 (54945 Rev 1.14):
* Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated
* Added bits to 80000001/ecx (amd).
* Added bits to 80000007/edx, 8000000a/edx, 8000001a/eax,
* Added 80000007/ebx, 80000007/ecx, 80000008/ebx.
* Added tentative 8000001f descriptions.
2018-04-20 - firstname.lastname@example.org
- Update to new upstream release 20180419
* Added synth decoding for AMD Zen, Pentium Silver (Gemini
Lake), Xeon Scalable (Bronze, Silver, Gold, Platinium)
(Skylake), Core X-Series (Skylake-X), Bay Trail D0, Bay Trail
A0, Xeon E7-4800/8800 (Broadwell-EX B0), Xeon D-1500N
(Broadwell-DE A1), Bay Trail-I (E3800), Avoton C0 stepping.
* Corrected synth decoding for Bay Trail-M C0 steppings.
* Added new Intel 1b leaf from Intel Architecture.
* Added various bit fields.
2017-01-23 - email@example.com
- Update to new upstream release 20170122
* Added synth decoding for Intel Knights Landing B0.
* Added new synth decodings for Intel Kaby Lake.
* Fixed synth decodings for AMD Steamroller and Jaguar.
* Added synth decodings for AMD Puma and Excavator.
* For (6,15),(0,2) Piledriver processors, detect FX series and
report it as Vishera instead of Abu Dhabi/Seoul/Delhi.
* Added general microarchitecure names for AMD (e.g.
Piledriver) in addition to specific core names (e.g. Trinity)
for later generation processors. If I have trouble
remembering these, it seems likely other people do too.
* Added synth decoding for Quark X1000.
* Added Intel Atom Z2760 (Clover Trail).
* Added extra synth decodings for some Ivy Bridge and Sandy
2016-12-02 - firstname.lastname@example.org
- Update to new upstream release 20161201
* Fixed bugs in the subleaf walks for 0x8000001d (AMD cache
information) and 0x40000003 (Xen hypervisor information) because
the code for them was under wholly the wrong loops.
2016-11-15 - email@example.com
- Update to new upstream release 20161114
* cpuid.c: Added -l/--leaf and -s/--subleaf options to cause
cpuid to dump just the specified leaf and subleaf. If
- s/--subleaf is not specified, it is assumed to be 0. The
intended purpose for this is to display raw dumps of
* cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and
CLWB decoding to 7/ebx.
* cpuid.c: Added AVX512VBMI to 7/ecx.
* cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring
* cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx.
* cpuid.c: Added 0x15/ecx nominal core crystal clock decoding.
* cpuid.c: In print_17_0_ebx, corrected reversed scheme
* cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0
* cpuid.c: Added synth decoding comment about Braswell D1
stepping, but its stepping number is not documented.
* cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake
* cpuid.c: Added synth decoding for Apollo Lake processors.
* cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake
* cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags.
* cpuid.c: Add Knights Mill (KNM) CPUID.